1. Technical Field
The present invention relates to memory devices in general, and in particular to embedded dynamic random access memory devices. Still more particularly, the present invention relates to a method and apparatus for accessing a banked embedded dynamic random access memory device.
2. Description of the Prior Art
Generally speaking, many different types of memory devices are employed within a digital computer system. One type of memory devices that is well-known in the art is dynamic random access memory (DRAM) devices. DRAM devices are commonly utilized for storing large increments of data, and the stored data can be accessed in any order. However, a DRAM device cannot be accessed when the DRAM device is being refreshed. Another type of memory devices that is well-known in the art is static random access memory (SRAM) devices. SRAM devices store information in logic circuits known as flip-flops that retain data without requiring any refresh. Thus, although SRAM devices do not have delay states associated to refresh cycles such as DRAM devices, SRAM devices are more complex than DRAM devices.
Yet another type of memory devices is called embedded DRAM devices. Embedded DRAM devices are a type of memory devices having both memory cells and their respective control circuits formed on a single semiconductor chip. Embedded DRAM devices are capable of transferring a large quantity of data at a very high speed. Because of their relatively high processing speed and storage capacity, embedded DRAM devices have been commonly employed in various high-end data processing systems, such as graphics processing systems. In addition, embedded DRAM devices can provide a processor a faster access to a relatively large capacity of on-chip memory at a lower cost than that currently available using conventional embedded SRAM devices and/or electrically erasable programmable read only memory (EEPROM) devices.
Both DRAM devices and embedded DRAM devices are formed in memory arrays having multiple memory locations. Each memory location of the memory arrays is identified by its memory address. When a memory location of the memory array is to be accessed, the address of the memory location can be provided to a decoder circuitry of the memory device, as is well-known in the art. The decoder circuitry decodes the address signal applied thereto in order to permit access to the memory location identified by the address signal. Typically, multiple banks of an embedded DRAM device may be placed together such that a single embedded DRAM controller can provide access control to each bank of the embedded DRAM device and routes addresses to a corresponding bank of memory within a banked cache memory.
The present disclosure provides an improved method for accessing a banked embedded DRAM device.
In accordance with a preferred embodiment of the present invention, an apparatus for accessing a banked embedded dynamic random access memory (DRAM) device comprises a general functional control logic and a bank RAS controller. The general functional control logic is coupled to each bank of the banked embedded DRAM device. Coupled to the general functional control logic, the bank RAS controller includes a rotating shift register having multiple bits. Each bit within the rotating shift register corresponds to each bank of the banked embedded DRAM device. As such, a first value within a bit of the rotating shift register allows accesses to an associated bank of the banked embedded DRAM device, and a second value within a bit of the rotating shift register denies accesses to an associated bank of the banked embedded DRAM device.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.